This invention relates generally to analog-to-digital converters, and more particularly, to encoding techniques employed to minimize errors arising in the conversion process. One of the most basic devices for the conversion of analog signals to digital form is the parallel analog-to-digital converter, in which an analog input signal is simultaneously compared with a large number of reference signals, representing each step in the range of the converter. For a converter having an n-bit digital output, there are 2.sup.n -1 reference levels and a like number of comparator circuits. For example, in an eight-bit converter there are 255 comparators, and 255 reference levels corresponding to the incremental steps between zero and a full-scale input value.
When an input signal is applied to the comparators, those having as inputs reference levels less than the input signal will produce an output signal of the same binary state, for example a logical "one" output, while the remainder will have an output of the opposite state, for example a logical "zero." For this reason, the output code is sometimes referred to as a thermometer code. The desired digital output can be obtained as the sum of the individual comparator outputs. For example, if a half-scale input signal is applied to the conversion circuit, providing logical "one" outputs from 128 of the comparators, the desired digital output signal is then 128, or, in fractional form, is a digital quantity proportional to 128/256. Implementation of an adder to count the number of "one" comparator outputs is not a simple matter, however, and virtually all higher-resolution parallel analog-to-digital converters built today rely on the detection of a single one-to-zero transition in the array of comparator outputs. Once the transition is located, it is converted to a desired digital code in a read-only memory circuit.
A potential for error exists in this conversion approach, however, since two or more one-to-zero transitions may occur over the array of comparator outputs. Multiple transitions may be caused by any of a variety of factors, such as rapidily slewing input signals, or non-matching comparator characteristics. If a conventional approach is used to convert from a one-in-n transition code to a corresponding binary code, the application of two transition codes will result in an output code that is the logical OR of two codes, only one of which is correct. The difference between this composite output and the correct binary code equivalent to the input signal varies from zero to more than fifty percent of full-scale, depending on the specific codes and input signals.
A common solution to this problem is to employ a well known binary code known as Gray code, instead of standard binary code, when converting from the one-in-n code obtained in the detection of a transition. The inherent difficulty with standard binary code, and the advantages of Gray code, can be appreciated from a simple example. Suppose that two one-to-zero transitions are detected and that they are one bit position apart. In standard binary code, the two transitions might translate into codes of 00000010 and 00000011, for example, corresponding to decimal values of 2 and 3, respectively. The logical OR of these two codes is 00000011, which is either exactly equal to the correct result, or is one bit in error. Suppose, however, that the two transitions were instead equivalent to binary codes of 01111111 and 10000000, corresponding to decimal values of 127 and 128. When these codes are ORed together, the result is 11111111, or 255 decimal. The error is therefore 01111111 or 10000000, depending on which of the transitions is the correct one. The error expressed as a decimal number is 127 or 128, which is approximately one hundred percent of the correct value and fifty percent of the full-scale value.
In Gray code, each step or increment of the code results in a change of state at only one bit position. If two adjacent one-to-zero transitions were detected, i.e. with a bit separation of one, use of the Gray code would limit the error to one part in 2.sup.n. For example, the Gray-code forms of the decimal numbers 127 and 128 are 01000000 and 11000000, respectively. When these codes are ORed together, the result is 11000000. In general, then, the logical OR of two adjacent Gray codes is always equal to one of the two codes. Therefore, the error will be either zero, if the result of the ORing operation is the correct code, or will be one part in 2.sup.n, where n is the number of bit positions in the code. Use of the Gray code also provides protection, but to a lesser degree, when the detected transitions are separated by more than one bit position.
In the most commonly used scheme for transition detection, the comparator outputs are connected as inputs to an array of AND gates, in such a manner as to generate a logical "one" output only at the transition point. In this arrangement of AND gates, it is impossible to obtain an indication of two transitions separated only by one bit position. In other words, the error best protected against by the use of Gray code cannot occur in the most commonly used transition detection scheme. It is therefore important to examine the affect of Gray code on multiple transitions separated by more than one bit position.
It happens that the use of Gray code does not eliminate or minimize errors resulting from transitions separated by two or more bit positions, and there is therefore a significant need for a parallel analog-to-digital converter in which such errors are greatly reduced. The present invention fulfills this need.